1. Field of the Invention
The present invention relates to semiconductor memory devices which can be simultaneously tested even when the number of them is large and a semiconductor wafer on which the semiconductor memory devices are formed.
2. Description of the Background Art
A semiconductor memory device (also called a xe2x80x9csemiconductor memory chipxe2x80x9d) on which memory cells for inputting/outputting data are arranged in a matrix is subjected to processes shown in FIG. 22 and then shipped. Specifically, referring to FIG. 22, a wafer process for forming a number of semiconductor memory chips on a semiconductor wafer such as a silicon (Si) wafer by an LSI process is performed (step S1). At a stage when the wafer process is finished, as shown in FIG. 23, a semiconductor wafer 700 has device areas 701 on which the semiconductor memory chips are formed and areas 702 on which no semiconductor memory chip is formed. The device areas 701 are arranged in a grid pattern.
An operation test for each of the semiconductor memory chips is conducted on the semiconductor wafer on which the semiconductor memory chips are formed as shown in FIG. 23 (step S2). After that, semiconductor memory chips determined as non-defective by the operation test are separated by cutting the semiconductor wafer 700 along the areas 702 in which no semiconductor memory chip, and an assembling process of packaging the chips is carried out (step S3). In a packaged state, an operation test is conducted again on each of the semiconductor memory chips (step S4), and only the semiconductor memory chips which passed the operation test are shipped.
The operation tests in step S2 and S4 are, as shown in FIG. 24, a writing test (step S5) for writing data into each of the memory cells and a reading test (step S6) for reading the written data and confirming that the read data coincides with the written data.
The operation test on each of the semiconductor memory chips is carried out by, as shown in FIG. 25, connecting a plurality of semiconductor memory chips to a tester. A tester 800 has a signal generating circuit 801, an address generating circuit 803, data generating circuits 805, 809, 813, and 817, determining circuits 807, 811, 815, and 819, drivers 802, 804, 806, 810, 814, and 818, and comparators 808, 812, 816, and 820. The signal generating circuit 801 generates a chip enable signal /CE for activating semiconductor memory chips 901 to 904. The driver 802 converts the chip enable signal /CE generated by the signal generating circuit 801 to a voltage value indicative of the H (logical high) level or the L (logical low) level and outputs the voltage value to the semiconductor memory chips 901 to 904. The address generating circuit 803 generates an address for designating one of memory cells (not shown) arranged in a matrix in each of the semiconductor memory chips 901 to 904. The driver 804 converts the address generated by the address generating circuit 803 into a voltage value indicative of the address and outputs the voltage value to the semiconductor memory chips 901 to 904.
The data generating circuits 805, 809, 813, and 817 generate data to be written into the semiconductor memory chips 901 to 904 at the time of the writing test in the operation test. Each of the drivers 806, 810, 814, and 818 converts the data generated by the data generating circuits 805, 809, 813, and 817 into a voltage value indicative of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d and outputs the voltage value to the semiconductor memory chips 901 to 904, respectively.
Each of the comparators 808, 812, 816, and 820 compares data read from the semiconductor memory chips 901 to 904 with a predetermined level at the time of the reading test in the operation test and converts the data to the logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Each of the determining circuits 807, 811, 815, and 819 compares data supplied from the comparators 808, 812, 816, and 820 with data generated at the time of the writing test by the data generating circuits 805, 809, 813, and 817 and determines whether the read data coincides with the write data or not.
The semiconductor memory chip 901 has a control terminal 905, an address terminal 906, and a data terminal 907. The semiconductor memory chip 902 has a control terminal 908, an address terminal 909, and a data terminal 910. The semiconductor memory chip 903 has a control terminal 911, an address terminal 912, and a data terminal 913. The semiconductor memory chip 904 has a control terminal 914, an address terminal 915, and a data terminal 916. The control terminals 905, 908, 911, and 914 are terminals for supplying the chip enable signal /CE to the semiconductor memory chips 901 to 904, respectively. The address terminals 906, 909, 912, and 915 are terminals for supplying an address to the semiconductor memory chips 901 to 904, respectively. The data terminals 907, 910, 913, and 916 are terminals for inputting/outputting data from/to the semiconductor memory chips 901 to 904, respectively.
In FIG. 25, although not shown in detail, each of the address terminals 906, 909, 912, and 915 is comprised of 22 terminals, and each of the data terminals 907, 910, 913, and 916 is comprised of 16 terminals. FIG. 25 shows a case where the operation test is conducted simultaneously on the four semiconductor memory chips 901 to 904.
Each of the semiconductor memory chips 901 to 904 has an activating/inactivating circuit 920 shown in FIG. 26. Referring to FIG. 26, the activating/inactivating circuit 920 has inverters 921 to 923. The chip enable signal /CE outputted from the driver 802 of the tester 800 is supplied via each of the control terminals 905, 908, 911, and 914 of the semiconductor memory chips 901 to 904 to the activating/inactivating circuit 920. The activating/inactivating circuit 920 inverts the logic of the supplied chip enable signal /CE three times, that is, inverts the logic of the supplied chip enable signal /CE and outputs the inverted logic. When the chip enable signal /CE of the L level is entered, the activating/inactivating circuit 920 therefore outputs a signal of the H level to activate the semiconductor memory chips 901 to 904. When the chip enable signal /CE of the H level is entered, the activating/inactivating circuit 920 outputs a signal of the L level to make the semiconductor memory chips 901 to 904 inactive.
Referring to FIGS. 25 and 27, an operation of conducting an operation test simultaneously on the semiconductor memory chips 901 to 904 will be described. In a period T1, data is written to the semiconductor memory chips 901 to 904. In a period T2, data is read from the semiconductor memory chips 901 to 904.
In the period T1, the signal generating circuit 801 in the tester 800 generates the chip enable signal /CE of the L level, and the driver 802 converts the signal to a voltage value indicative of the chip enable signal /CE of the L level and outputs the voltage value. The chip enable signal /CE of the L level is supplied to the semiconductor memory chips 901 to 904 via the control terminals 905, 908, 911, and 914 to activate each of the semiconductor memory chips 901 to 904. After that, a write enable signal /WE is generated by a signal generating circuit (not shown) and supplied from a control terminal (not shown) to make the semiconductor memory chips 901 to 904 enter a data writable state.
The address generating circuit 803 generates an address xe2x80x9cAddressxe2x80x9d to designate one of the memory cells arranged in the matrix in each of the semiconductor memory chips 901 to 904, and the driver 804 converts the generated address xe2x80x9cAddressxe2x80x9d to a voltage value and outputs the voltage value. The address xe2x80x9cAddressxe2x80x9d outputted from the tester 800 is supplied via the address terminals 906, 909, 912, and 915 to the semiconductor memory chips 901 to 904, respectively, which are sequentially activated in accordance with the address xe2x80x9cAddressxe2x80x9d indicative of a plurality of memory cells included in the semiconductor memory chips 901 to 904. After that, the data generating circuit 805 generates data xe2x80x9cDataxe2x80x9d to be written to the semiconductor memory chip 901, and the driver 806 converts the generated data xe2x80x9cDataxe2x80x9d into a voltage value and the outputs the voltage value. The data xe2x80x9cDataxe2x80x9d outputted from the tester 800 is supplied via the data terminal 907 to the semiconductor memory chip 901 and is written in the activated memory cell.
Similarly, the data generating circuits 809, 813, and 817 generate write data xe2x80x9cDataxe2x80x9d, and the drivers 810, 814, and 818 convert the data xe2x80x9cDataxe2x80x9d to a voltage value and outputs the voltage value. The data xe2x80x9cDataxe2x80x9d outputted from the tester 800 is supplied via the data terminals 910, 913, and 916 to the semiconductor memory chips 902 to 904 and is written in the activated memory cells.
After finishing the writing of the data xe2x80x9cDataxe2x80x9d to the semiconductor memory chips 901 to 904, in the period T2, the data xe2x80x9cDataxe2x80x9d is read from the semiconductor memory chips 901 to 904. In this case as well, first, the chip enable signal /CE is generated by the signal generating circuit 801 in the tester 800, and the semiconductor memory chips 901 to 904 are activated by a method similar to the above. The signal generating circuit (not shown) in the tester 800 generates the output enable signal /OE, and the semiconductor memory chips 901 to 904 receive the output enable signal /OE from the control terminal (not shown) and enter a data xe2x80x9cDataxe2x80x9d outputtable state. After that, the address generating circuit 803 generates the address xe2x80x9cAddressxe2x80x9d. The generated address xe2x80x9cAddressxe2x80x9d is supplied to the semiconductor memory chips 901 to 904 by a method similar to the above to activate each of the memory cells in the semiconductor memory chips 901 to 904. The semiconductor memory chip 901 outputs data Data0 read from each memory cell to the comparator 808 from the data terminal 907. The comparator 808 compares the data Data0 received from the semiconductor memory chip 901 with a predetermined level to thereby convert the data to data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, and outputs the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d to the determining circuit 807. The determining circuit 807 compares the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d from the comparator 808 with the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d generated by the data generating circuit 805 to determine whether the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d written in the semiconductor chip 901 is read or not.
The semiconductor memory chip 902 outputs the data Data1 read from the memory cell from the data terminal 910 to the comparator 812. The comparator 812 compares input data Data1 with a predetermined level, converts it to data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, and outputs the resultant data to the determining circuit 811. The determining circuit 811 compares the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d from the comparator 812 with the data xe2x80x9c1 or xe2x80x9c0xe2x80x9d generated by the data generating circuit 809, thereby determining whether the dataxe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d written in the semiconductor memory chip 902 has been read or not.
Data Data2 and Data3 read from the semiconductor memory chips 903 and 904 is also subjected to the determining operation of the determining circuits 815 and 819, respectively, in a manner similar to the above.
In the conventional test method, however, when the number of semiconductor memory chips to be tested simultaneously is increased, it is necessary to increase the number of drivers for data and the number of pins of comparators in the tester. In some testers, the number of pins cannot be increased due to restriction on the tester. Consequently, a problem such that the efficiency of a test cannot be increased occurs.
When a new tester has to be purchased to increase the number of pins for testing, investment is newly required, and a problem such that the manufacturing cost of the semiconductor memory chip increases arises.
It is therefore an object of the invention to provide semiconductor memory devices which can be simultaneously tested even when the number of them is large without increasing the number of pins in a tester and a semiconductor wafer on which the semiconductor memory devices are formed.
According to the invention, a semiconductor memory device has: a plurality of memory cells: input/output terminals for inputting/outputting data; an address terminal for receiving an address for making each of the plurality of memory cells active; a plurality of control terminals provided in correspondence with a plurality of control signals, for receiving the plurality of control signals; an activating/inactivating circuit for receiving the plurality of control signals and outputting an activation signal or an inactivation signal in accordance with logic of the plurality of control signals; an address decoder for decoding an address supplied via the address terminal on the basis of the activate signal and making each of the plurality of memory cells active on the basis of the decoded address; and an input/output circuit for inputting/outputting data to/from the memory cell activated by the address decoder on the basis of the activate signal.
Preferably, the activating/inactivating circuit outputs the activation signal when all of the plurality of control signals have a first logic, and outputs the inactivation signal when at least one of the plurality of control signals has a second logic.
Preferably, in normal operation, the activating/inactivating circuit outputs the activation signal or the inactivation signal in accordance with the logic of one of the plurality of control signals.
Preferably, the activating/inactivating circuit outputs the activation signal or the inactivation signal by performing an operation to obtain a logical product of the plurality of control signals.
Preferably, the plurality of control signals are a chip enable signal as one of the control signals and a selection signal, and the selection signal is held in the first logic.
Preferably, the input/output circuit includes an output circuit for outputting output data from each of the plurality of memory cells as a digital signal.
According to the invention, a semiconductor memory device has: a plurality of memory cells: input/output terminals for receiving/outputting data; an address terminal for receiving an address for making each of the plurality of memory cells active; a first control terminal for receiving a first control signal; a second control terminal for receiving a second control signal; an activating/inactivating circuit for receiving the second control signal as a logical signal when the first control signal has a first logic and outputting an activation signal or an inactivation signal in accordance with the logic of the second control signal, for receiving the second control signal as an analog signal when the first control signal has a second logic and outputting the activation signal or the inactivation signal in accordance with the value of the analog signal; an address decoder for decoding an address supplied via the address terminal on the basis of the activation signal and making each of the plurality of memory cells active on the basis of the decoded address; and an input/output circuit for inputting/outputting data to/from the memory cell activated by the address decoder on the basis of the activation signal.
Preferably, the activating/inactivating circuit includes: a selection signal generating circuit for generating a selection signal of a first or second logic in accordance with the value of the analog signal; a selecting circuit for selecting the second control signal as the logic signal when the first control signal has the first logic and selecting the selection signal when the first control signal has the second logic; and a signal outputting circuit for outputting the activation signal when the selected second control signal or selection signal has the first logic, and outputting the inactivation signal when the selected second control signal or selection signal has the second logic.
Preferably, the selection signal generating circuit has: an AD converter for converting the analog signal to a digital signal having a digital value which varies according to the value of the analog signal; and a decoding circuit for generating the selection signal on the basis of the digital signal.
Preferably, in normal operation, the first control signal is held in the first logic.
Preferably, the input/output circuit includes an output circuit for outputting output data from each of the plurality of memory cells as a digital signal.
According to the invention, a semiconductor wafer including a plurality of first semiconductor memory devices arranged in the (2nxe2x88x921)th row (where n is a natural number), a plurality of second semiconductor memory devices arranged in the 2n-th row, and cutting areas, wherein each of the plurality of first semiconductor memory devices includes: a plurality of first memory cells; a first input/output terminal for inputting/outputting data; a first address terminal for receiving an address for making each of the plurality of first memory cells active; a first control terminal for receiving a first control signal for generating an activation signal at the time of writing the data; a second control terminal for receiving a second control signal for generating an activation signal at the time of reading the data; a first activating/inactivating circuit for outputting an activation or inactivation signal in accordance with the logic of the first or second control signal; a first address decoder for decoding an address received via the address terminal on the basis of the activation signal and activating each of the plurality of memory cells on the basis of the decoded address; and a first input/output circuit for inputting/outputting data from/to a memory cell activated by the address decoder on the basis of the activation signal, and each of the plurality of second semiconductor memory devices includes: a plurality of second memory cells; a second input/output terminal for receiving/outputting data; a second address terminal for receiving an address for making each of the plurality of second memory cells active; a third control terminal connected to the second control terminal by an interconnection via the cutting area; a second activating/inactivating circuit for outputting an activation signal or an inactivation signal in accordance with logic of the second control signal; a second address decoder for decoding an address supplied via the address terminal on the basis of the activation signal and making each of the plurality of memory cells active on the basis of the decoded address; and a second input/output circuit for inputting/outputting data to/from the memory activated by the address decoder on the basis of the activation signal.
Preferably, the first activating/inactivating circuit outputs the activation signal when the first control signal has a first logic or when the second control signal has a first logic, and the second activating/inactivating circuit outputs the activation signal when the second control signal has a second logic.
Preferably, the first activating/inactivating circuit outputs the inactivation signal when the first and second control signals have a second logic, and the second activating/inactivating circuit outputs the inactivation signal when the second control signal has a first logic.
According to the invention, a semiconductor wafer having a plurality of areas each including a plurality of semiconductor memory devices, and a cutting area, wherein the cutting area includes a selection signal generating circuit for generating a selection signal for activating a plurality of semiconductor memory devices included in each of the plurality of areas in response to logic of a plurality of first control signals, and each of the plurality of semiconductor memory devices includes: a plurality of memory cells; an input/output terminal for inputting/outputting data; an address terminal for receiving an address for making each of the plurality of first memory cells active; a control terminal for receiving the selection signal generated by the selection signal generating circuit; an activating/inactivating circuit for receiving the selection signal and outputting an activation or inactivation signal in response to the logic of the selection signal; an address decoder for decoding an address received via the address terminal on the basis of the activation signal and activating each of the plurality of memory cells on the basis of the decoded address; and an input/output circuit for inputting/outputting data from/to a memory cell activated by the address decoder on the basis of the activation signal.
Preferably, the selection signal generating circuit generates selection signals of the number corresponding to the plurality of areas.
Preferably, at the time of writing data, the selection signal generating circuit generates the selection signal so as to simultaneously make all of semiconductor memory devices active, and at the time of reading data, generates the selection signal so as to make a plurality of semiconductor memory devices included in each of the plurality of areas on the area unit basis.
Preferably, the activating/inactivating circuit outputs the activation signal when the selection signal has a first logic.
Preferably, each of the plurality of semiconductor memory devices has one more control terminal for receiving a chip enable signal, and the activating/inactivating circuit outputs the activation signal or the inactivation signal by performing an operation to obtain a logical product of the chip enable signal and the selection signal.
According to the invention, a semiconductor wafer having a plurality of semiconductor memory devices each including a plurality of memory cells and a cutting area, wherein each of the plurality of semiconductor memory devices includes: an output circuit for outputting read data from the plurality of memory cells as a digital signal; and an input circuit for writing write data into the plurality of memory cells, and the cutting area includes: an input/output switching circuit for converting a digital signal from the output circuit into an analog signal, outputting the read data as an analog signal, and supplying the write data to the input circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.